Anchored by the world-class TimeCraft static timing analyzer, Incentia offers a complete tool suite for static timing, signal integrity, and power analysis, as well as timing and constraint checking, debugging, and validation.

TimeCraft is a full-chip, gate-level static timing analyzer (STA) for timing sign-off. It is the fastest STA available in the market and has been proven through numerous customer tape-outs. TimeCraft has demonstrated unparalleled advantages in runtime and capacity that dramatically reduce total timing verification turnaround time. TimeCraft offers an advanced OCV feature that provides an effective solution to addressing the effects of statistical on-chip process variations. The advanced OCV uses variable derating factors based on the logic level and physical location to select the optimal derating factor for each timing path. This results in fewer timing violations, which allows design teams to rapidly achieve timing closure. The native engine-based implementation approach is easy to use and delivers unmatched performance in runtime and memory usage.

Incentia's signal integrity (SI) analysis is built on top of its fast and tape-out proven TimeCraft timing engine as an integrated timing and signal integrity analysis solution. TimeCraft-SI contains both crosstalk and noise analysis. To eliminate the inaccuracy caused by MVS (Model Voltage Sources), TimeCraft-SI supports both CCS and ECSM library formats. For crosstalk analysis, TimeCraft-SI has invented unique algorithms that consider cell and interconnect delta delays with finest granularity, and thus gives the most accurate analysis results. Noise Analysis is done using a dedicated engine that accurately captures the behavior of static noise.

ConstraintCraft is Incentia's solution for managing complex constraints. It consists of a Constraint Checker, Debugger, and Validator. The Constraint Checker checks constraint completeness, correctness, conflicts, and redundancy. The Constraint Debugger allows designers to debug timing exceptions and diagnose no timing paths. The Constraint Validator performs false path and bridge fault validation. These capabilities provide an effective and easy-to-use solution to clean, debug, and validate constraints, improving constraint quality and reducing constraint verification turnaround time.

TimeCraft-PCA is a highly efficient power analysis solution for both gate-level and RTL-level designs. It supports both vectorless and vector-based (i.e. activity-file based) power analyses. It can handle extremely large activity files for full-chip power analysis with FSDB, VCD and SAIF inputs. It also supports multiple activity files. TimeCraft-PCA can analyze and report dynamic power, state-dependent and power-dependent (SDPD) internal power, X-transition power and glitch power, SDPD leakage power, clock tree power, average power, and peak power.

Built on top of TimeCraft timing engine, ECOCraft is Incentia's ECO solution for post-layout hold time fixing and leakage power reduction. The 8X to 10X speedup over other solutions enables the faster turnaround time and design closure at the later tape-out stage.

ECOCraft-timing is a post layout hold time optimization tool. Once your design is free of setup time violations, it tries to fix hold time violations under Multi-Mode Multi-Corner (MMMC) scenario simultaneously, without violating setup times. It adopts an innovative algorithm that fixes the largest amount of hold time violations with a minimal number of delay insertions. The impact to layout is therefore minimized. Due to the tightly integrated ECO and TimeCraft timing engine, runtime is 8X to 10X faster than other existing solutions. To further reduce total turnaround time, all the corresponding MMMC processes can be distributed to network machines and run in parallel.

Leakage power consumption becomes significant in nanometer designs. Many applications, such as mobile devices, need to reduce leakage power. ECOCraft-Power is a post layout in-place leakage power reduction tool. It utilizes multi-threshold libraries and can further reduce 10% to 20% leakage power from already optimized designs. Setup times are preserved through the use of a highly accurate delay estimation algorithm. Since it uses the in-place optimization technique, ECOCraft-Power replaces low-threshold cells with their high-threshold counterparts with the same layout footprints on the spots. There is no need to re-do the time consuming place and route. In general, ECOCraft-Power runs 5X to 10X faster than other existing solutions due to its built-in TimeCraft timing engine. MMMC flow is also supported to reduce total turnaround time.

DesignCraft is a complete logic synthesis tool with integrated capability to optimize for area, power, timing, and design-for-testability (DFT). DesignCraft is based upon Incentia's proven TimeCraft timing engine to ensure consistent timing results. DesignCraft specializes in low power and leakage power reductions. Through its multiple patented technologies in area, power, and timing optimization, DesignCraft produces the most aggressive area reduction and low power results, with unmatched advantages in runtime and capacity.

TestCraft is Incentia's DFT synthesis, which can be used as an integrated option of DesignCraft or in a stand-alone manner. TestCraft offers rich features in DFT rule checking and fixing, scan cell replacement and optimization, various scan chaining schemes, and comprehensive DFT preview analysis and reports. Through its patented SEDAN (STA Enhanced DFT Analysis) and ABS (Affinity Based Scan Optimization) technologies, TestCraft runs several times faster than other DFT synthesis solutions, while preserving timing quality and increasing fault coverage on your designs.