TimeCraft is a full-chip, gate-level static timing analyzer (STA) for timing sign-off. It is the fastest STA available in the market. Its rich features include comprehensive timing checks and reports, a built-in delay calculator, multiple supply voltage analysis, multi-task for multi-corner multi-mode analysis, and advanced PLL handling.

TimeCraft further extends its technology lead in nanometer design timing analysis with a new advanced on-chip-variation (OCV) analysis. Traditional OCV uses a constant derating factor which imposes a heavy performance penalty on nanometer designs. These penalties include reduced performance, larger die sizes, and longer design cycles. TimeCraft's advanced OCV uses variable derating factors based on logic level and physical location to select the optimal derating factor for each timing path. This results in fewer timing violations, and allows design teams to rapidly achieve timing closure.

The native-engine based implementation approach is easy to use and delivers unmatched performance in runtime and memory. TimeCraft's advanced OCV provides an effective alternative to the difficult problem of using statistical analysis to model process variations.

TimeCraft has demonstrated unparalleled advantages in runtime and capacity that dramatically reduce total timing verification turnaround time. It is a proven best-in-class STA through numerous successful customer tape-outs.

Incentia's signal integrity (SI) analysis is built on top of its fast and tape-out proven TimeCraft timing engine as an integrated timing and signal integrity analysis solution. TimeCraft-SI contains both crosstalk and noise analysis. To eliminate the inaccuracy caused by MVS (Model Voltage Sources), TimeCraft-SI relies on a proprietary Current-source Current-bias Model (ICCM) for crosstalk analysis. Additionally, traditional net-based crosstalk analysis considers only one delta delay on each net, regardless what timing arc drives the net. TimeCraft-SI applies a timing-arc based analysis, and considers different delta delays based on the timing arc that drives the timing path. This gives the most accurate crosstalk analysis results. Noise Analysis is done using a dedicated noise analysis engine that accurately captures the behavior of static noise.

TimeCraft-CM is Incentia's solution for complex constraint management (CM). It consists of a constraint checker, a qualified SDC writer, and a constraint debugger. The constraint checker checks constraint files for completeness, correctness, and conflicts. It also eliminates redundant constraints. The SDC writer then produces a set of optimized constraints. The constraint debugger allows designers to identify the optimal timing exceptions in complex environment on the fly. These capabilities provide an effective and easy-to-use mechanism to purify and generate qualified constraints and thus greatly shorten total constraint management and timing verification turnaround time.

DesignCraft is a complete logic synthesis tool with integrated capability to optimize for area, power, timing, and design-for-testability (DFT). DesignCraft is based upon Incentia's proven TimeCraft timing engine to ensure consistent timing results. DesignCraft specializes in low power and leakage power reductions. Through its multiple patented technologies in area, power, and timing optimization, DesignCraft produces the most aggressive area reduction and low power results, with unmatched advantages in runtime and capacity.

TestCraft is Incentia's DFT synthesis, which can be used as an integrated option of DesignCraft or in a stand-alone manner. TestCraft offers rich features in DFT rule checking and fixing, scan cell replacement and optimization, various scan chaining schemes, and comprehensive DFT preview analysis and reports. Through its patented SEDAN (STA Enhanced DFT Analysis) and ABS (Affinity Based Scan Optimization) technologies, TestCraft runs several times faster than other DFT synthesis solutions, while preserving timing quality and fault coverage on your designs.